1. Field of the Invention
This invention relates to a synchronous circuit for a digital transmission system, and more particularly to a synchronous circuit for use with a bit stream wherein the number of bits in a frame varies periodically in order to keep a transmission rate fixed in average and each frame includes information of the bit number called padding.
2. Description of the Related Art
Various synchronous circuits of the type mentioned are conventionally known, and an exemplary one of such synchronous circuits is a synchronous circuit for the layers 1 and 2 of a bit stream according to a compression and decompression system for a digital audio signal standardized by the ISO/IEC 11172-3 (hereinafter referred to as MPEG/Audio system). Details of the MPEG (Moving Picture Experts Group)/Audio system are described in the standards mentioned above.
A frame of the MPEG/Audio system is roughly divided into two portions including a header portion and a data portion. The header portion includes information of a synchronism pattern, a layer, a bit rate Br, a sampling frequency Fs, a padding and so forth. The synchronism pattern is formed from successive 1s of 12 bits, and the layer represents what method from among three compression methods defined in the MPEG/Audio system has been used to compress the frame. The number of slots of the frame is calculated from the layer, the bit rate Br, the sampling frequency Fs and the padding. The slot number is normally given by an expression (Br/N).multidot.(L/Fs), where N is the number of bits included in one slot, and L is the number of samples of the digital signal of the sampling frequency Fs included in one frame of the bit stream. The number of bits included in one slot is determined to be 32 bits for the layer 1, but 8 bits for the layers 2 and 3.
As an example, if the number of bits of one frame when the layer is 2, the bit rate Br is 192 kHz and the sampling frequency Fs is 48 kHz is calculated in accordance with the expression given above, then, EQU (192.times.10.sup.3).multidot.(1,152/48.times.10.sup.3)=4,608
where 1,152 is the number of samples of one channel of the digital audio signal included in one frame. In this instance, the number of bits of one frame is an integral number.
As another example, if the number of bits of one frame when the layer is 2, the bit rate is 192 kHz and the sampling frequency is 44.1 kHz is calculated, then, EQU (192.times.10.sup.3).multidot.(1,152/44.1.times.10.sup.3)=5,015.5120 . . .
In this instance, the bit number of one frame is not an integral number. Meanwhile, in the layer 2 of the MPEG/Audio system, since one slot is determined to be 8 bits, the number of bits included in one frame must be a multiple of 8.
Therefore, frames each of which includes 5,008 bits or 5,016 bits, which are multiples of 8, are combined suitably so that an average bit number may be equal to 5,015.5102 . . . In the combining processing, a basic frame is first determined to include 5,008 bits, and an additional slot formed from 8 bits is defined. A frame which does not include the additional slot is formed from 5,008 bits, but another frame which includes the additional slot is formed from 5,016 bits. When the aforementioned padding is "0", the basic frame is selected, but when the padding is "1", the frame which includes the additional slot is selected. By selecting the padding values suitably between "0" and "1", the average bit number can be approximated to 5,015.5102 . . . which is a value between 5,008 and 5,016.
The factors upon which the slot numbers depend normally exhibit, upon high efficiency coding of successive digital audio signals, fixed values except the padding. However, the padding varies for each frame in order to approximate the average bit rate to a value designated by a bit rate value at the header portion. Since the length of a frame varies depending upon the padding value, also the interval between synchronism patterns varies.
Further, successive 1s of 12 bits which make the synchronism pattern may appear not only once, but may possibly appear also in the data portion.
Accordingly, it is not easy to detect a synchronism pattern of the bit stream described above, and a synchronism detection circuit designed for exclusive use is used for such detection.
FIG. 7 shows an example of a circuit for decompressing a compressed signal in synchronism with a bit stream. Referring to FIG. 7, the circuit shown includes a decompression processor 41 and a synchronism detector 42'. When the synchronism detector 42' detects a synchronizing bit train from a bit stream 10 inputted thereto, it outputs a start signal 11 to the decompression processor 41. Upon reception of the start signal 11, the decompression processor 41 performs decompression processing for the bit stream 10 in response to a clock signal 12 and outputs a PCM (pulse code modulation) signal 13. The synchronism detector 42' outputs a start signal 11 for each one frame, and the decompression processor 41 performs processing for one frame in response to each such start signal 11. Here, the synchronism detector 42' which is related to the present invention will be described in more detail.
An internal construction of the synchronism detector 42' is shown in FIG. 8. Referring to FIG. 8, the synchronism detector 42' shown includes a serial to parallel converter 42-1, a synchronism pattern detector 42-2, a selector 42-3, a header register 42-4, a frame counter 42-5, a header updating condition storage section 42-6, a synchronism discriminator 42-7 and a step-out discriminator 42-8.
In operation of the synchronism detector 42', the count value of the frame counter 42-5 is reset to 0, parallel data 27 which is an output signal of the serial to parallel converter 42-1 is reset to 0 and a header updating permission signal 20 is set in response to a reset signal 14.
The bit stream 10 is inputted as serial data to the synchronism detector 42' in synchronism with the clock signal 12, converted into parallel data 27 by the serial to parallel converter 42-1 and outputted to the synchronism pattern detector 42-2. The synchronism pattern detector 42-2 outputs a synchronism pattern detection signal 26 if a conformable value as data which forms a header including a synchronism pattern prescribed in accordance with the MPEG/Audio system is inputted thereto. The selector 42-3 selects one of the start signal 11 and the synchronism pattern detection signal 26 in response to the header updating permission signal 20. In particular, if the header updating permission signal 20 is in a set condition, then the synchronism pattern detection signal 26 is selected, but if the header updating permission signal 20 is in a reset condition, then the start signal 11 is selected. In an initial state, the header updating permission signal 20 is in a set condition, and consequently, the synchronism pattern detection signal 26 is selected and outputted as a latch signal 21 to the header register 42-4. In response to the latch signal 21, the header register 42-4 stores a layer, a bit rate, a sampling frequency and a padding which are outputted from the serial to parallel converter 42-1 and are values which define a frame length.
Further, in response to the latch signal 21, the frame counter 42-5 is reset, and counting of the number of clocks of the clock signal 12 is started. In the meantime, in response to the synchronism pattern detection signal 26, the header updating condition storage section 42-6 resets the header updating permission signal 20. After the header updating permission signal 20 is reset, a layer 22, a bit rate 23 and a sampling frequency 28 which are information necessary to determine the frame length to be outputted from the header register 42-4 are updated each time a start signal 11 is outputted.
The frame counter 42-5 calculates the number of bits of a frame from the layer 22, the bit rate 23, the sampling frequency 28 and a padding 24 outputted from the header register 42-4, and counts the clock signal 12 until the count value of it reaches the bit number.
It is to be noted that, when the sampling frequency is 32 kHz or 48 kHz, since the frame length always has a fixed value and no additional slot is involved, the padding value is ignored so that the counting end value of the frame counter 42-5 may not be influenced by an error in transmission of the padding value. After the frame counter 42-5 completes its counting processing of one frame, it outputs a counting end signal 25. When the counting end signal 25 and the synchronism pattern detection signal 26 are outputted simultaneously to the synchronism discriminator 42-7, the synchronism discriminator 42-7 outputs a start signal 11. Similar processing is performed also for the third and following frames, and a start signal is outputted if a counting end signal 25 is outputted simultaneously when a synchronism pattern is inputted as a bit stream.
If successive 1s of 12 bits are included by chance in the data portion and are detected as a synchronism pattern in error, then a meaningless value different from a frame length is substituted into the frame counter 42-5. Then, the probability that successive 1s of 12 bits may be inputted by chance at the time at which a counting end signal 25 is produced is very low. When a synchronism pattern detection signal 26 is not outputted simultaneously with a counting end signal 25, a step-out detection signal 29 is outputted from the step-out discriminator 42-8 and the header updating permission signal 20 to be outputted from the header updating condition storage section 42-6 is set, thereby returning to the initial condition. In short, when an erroneous synchronism pattern is detected as described above, a synchronous condition is lost once, and then a synchronism pattern is detected again.
In this manner, when a synchronous condition is established with an erroneous synchronism pattern, the synchronous condition is lost once and initialization is performed, but when a synchronous condition is established correctly, the synchronism pattern detection signal 26 is confirmed for each frame.
However, if, after a synchronous condition is established in the conventional synchronism detection circuit described above, an error in transmission occurs with the bit stream 10 and a synchronism pattern detection signal 26 is not outputted simultaneously with a counting end signal 25, then an initial condition is restored similarly to the case when an erroneous synchronism pattern is detected, and consequently, the synchronous condition is lost. When a synchronism pattern detection signal 26 is not outputted simultaneously with a counting end signal 25 in this manner, it is discriminated that an asynchronous or step-out condition is entered.
In order to reduce such step-out conditions caused by a transmission error as described above, such a general countermeasure to prevent a step-out condition may possibly be adopted wherein a discrimination of a step-out condition is made when the situation that a synchronism pattern detection signal 26 is not outputted simultaneously with a counting end signal 25 in this manner occurs successively two or more times. With the countermeasure, even if a synchronism pattern is not detected by an error, if another synchronism pattern is detected with a succeeding frame, then a synchronous condition is maintained.
However, if a header value necessary to determine a frame length is in error, then since the frame counter 42-5 outputs a counting end signal 25 with a value different from a frame length, the counting end signal 25 is produced at a time different from the time of the top of a next frame, resulting in loss of synchronism. In other words, even if the countermeasure described above is taken, a step-out condition is possibly entered as a result of an error in transmission.
Thus, the conventional synchronous circuit described above is disadvantageous in that, when an error in padding value which is information necessary to determine a frame length occurs on a transmission medium before a bit stream is transmitted to a reception circuit, since the number of bits or the number of slots of one frame is recognized in error, the output timing of a counting end signal 25 is displaced from a synchronism pattern detection signal 26, resulting in entering into a step-out condition.